1. Field of the Invention
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of trenched polysilicon gate formation, tungsten-plug contact completion, and implant-induced inter-metal dielectric for improved integrated circuit devices.
2. Description of the Prior Art
The conventional multi-level metallization process in the fabrication of Very Large Scale Integrated (VLSI) circuits suffers from a lack of planarization of the interlevel dielectric. The definition of sub-micron lines requires short wavelength photolithography at the cost of reduced depth of focus. Because of this reduced depth of focus, planarization of the layer to be exposed to photolithography is essential. An unplanarized layer requires a range of depths of focus which are not available in the sub-micron technology.
The step coverage of a metal layer formed by physical vapor deposition (PVD) is closely related to the morphology of the underlayer. More material is deposited on the "hump" than is deposited in the "valley." The larger the aspect ratio of the contact/via openings, the smaller the thickness of the metal sputtered onto the sidewalls and bottoms of the openings. For contact/via openings with a high aspect ratio larger than one, keyholes or voids naturally form in the openings and usually result in circuit failure of the contact/via opening.
In order to fill the contact/via openings with high aspect ratio of larger than one by a PVD method, a high deposition temperature or post-deposition thermal treatment is required. However, these methods suffer from difficulty of process control and sometimes the keyhole or void in the opening is inevitable. Because of these problems, the tungsten-plug process was introduced. The tungsten film can be deposited by chemical vapor deposition (CVD) with conformal step coverage. Alter blanket tungsten CVD and etchback, it is easy to obtain a planarized contact/via filling. Other candidates for this kind of filling include selective tungsten CVD, copper or silver CVD, as well as aluminum CVD. "An Advanced Four Level Interconnect Enhancement Module for 0.9 Micron CMOS" by C. A. Bollinger et al, VMIC Conference Proceedings, Jun. 12-13, 1990, c. 1990 by IEEE, pp.21-27 discusses the use of a tungsten plug for contact window filling.
Even after the metal layer is deposited to an acceptable planarized surface, the morphology still shows a moderate ruggedness after metal pattern definition. The metal thickness cannot be reduced because of circuit performance considerations, but the metal line width and spacing have been reduced considerably in high density VLSI circuits. The aspect ratio of metal line spacings for the deposition of the intermetal dielectric layer is typically larger than one in sub half-micron devices. The planarization of the intermetal dielectric has become an important issue.
Many kinds of intermetal dielectric formation have been adopted to obtain an acceptable planarization. One method is to deposit dielectric conformally and etchback anisotropically many times. Its drawback is throughput and lack of productivity. Another method is to form a layer of spin-on-glass between two CVD oxide layers. The presence of aluminum limits the cure temperature and the uncured moisture in spin-on-glass always results in poisoned via as well as poor adhesion between the CVD oxides. Recently, chemical mechanical polishing (CMP) has been developed to planarize this kind of dielectric layer as well as for the conducting layer. However, the CMP method suffers from many drawbacks such as a complex process, more particles, serious loading effect, long learning time, cost of ownership, maturity, etc.
Local oxidation of silicon is the conventional lateral isolation scheme. The conventional local oxidation process (LOCOS) is described in VLSI Technology, International Edition, by S. M. Sze, McGraw-Hill Book Company, NY, N.Y., c. 1988 by McGraw-Hill Book Co., pp. 473-474. A layer of silicon nitride is deposited over a pad oxide overlying a silicon substrate. The pad oxide is a thin thermal oxide which allows better adhesion between the nitride and silicon and acts as a stress relaxation layer during field oxide formation. The nitride and oxide layers are etched to leave openings exposing portions of the silicon substrate where the local oxidation will take place. A boron channel-stop layer is ion implanted into the isolation regions. The field oxide is grown within the openings and the nitride and pad oxide layers are removed. This completes the local oxidation.
A major drawback of conventional local oxidation is a lack of planarization of the oxidized surface of the substrate. Trench isolation methods solve this problem. Typically, deep narrow trenches are used to isolate one device from another. Shallow trenches are used to isolate elements within a device, and wide trenches are used in areas where interconnection patterns will be deposited. U.S. Pat. No. 5,294,562 to Lur et al teaches one method of trench isolation with global planarization. Patent application Ser. Nos. 08/127,061 now U.S. Pat. No. 5,372,968 issued on Dec. 13, 1994 to Water Lur el at, 08/126,87 now U.S. Pat. No. 5,366,925 issued on Nov. 22, 1994 to Water Lur, and 08/127,052 now U.S. Pat. No. 5,380,786 issued on May 3, 1994 to Water Lur et al, all filed on 9/27/93 teach other methods of trench isolation.
The articles, "Simulation of Sub-0.1-.mu.m MOSFET's with Completely Suppressed Short-Channel Effect," by Junko Tanaka et al, IEEE Electron Device Letters, Vol. 14, No. 8, August 1993, pp. 396-399 and "A New 0.25-.mu.m Recessed-Channel MOSFET with Selectively Halo-Doped Channel and Deep Graded Source/Drain," by W. H. Lee et al, IEEE Electron Device Letters, Vol. 14, No. 12, December 1993, pp. 578-580, discuss the improved performance and reliability of deep sub-micron devices afforded by trenched gates.
U.S. Patent to Matlock et al teaches the transformation of doped polysilicon or aluminum into an insulator by ion implanting oxygen or nitrogen for the purpose of selective deposition of tungsten or gold in contact/via openings. This method requires the use of a base layer, such as polysilicon. The contact/via formation is by selective deposition using the contact/via stud as a mask.